The present invention relates generally to electronic packaging, and more particularly, relates to a method for preparing the electrical interconnections of a chip carrier, including planarization, for subsequent joining to a semiconductor device.
Semiconductor devices can be connected to their supporting carrier by any number of methods. One particularly preferred method is called controlled collapse chip connection or simply C-4. In the C-4 method, small solder balls are formed on the input/outputs (I/Os) of the semiconductor device. The semiconductor device is joined to its supporting carrier by aligning the small solder balls on the semiconductor device with corresponding pads on the surface of the supporting carrier, followed by reflowing to cause bonding of the solder balls to the pads of the supporting carrier.
Ceramic chip carriers are a favored substrate for supporting semiconductor devices having C-4s. Ceramic chip carriers, however, suffer from camber and other surface irregularities resulting from their processing which leaves the joining surface of the ceramic substrate less than planar. Similar although less extreme variations can occur with organic chip carriers.
When connecting semiconductor devices having C-4s, variations in the planarity of the chip carrier can result in interconnection defects.
Accordingly, it would be desirable to have a method of preparing the electrical interconnections of a chip carrier to facilitate the subsequent joining thereto of a semiconductor device having C-4s.
Martin et al. IBM Technical Disclosure Bulletin, 23, No. 5, p. 1877, October 1980, the disclosure of which is incorporated by reference herein, disclose shaving the surface of a chip or wafer to expose solder balls previously encapsulated by polyimide. Additional solder is then deposited on the shaved solder balls. The shaving is not done for planarization since the chip or wafer surface is initially flat.
Pasch U.S. Pat. No. 5,468,681, the disclosure of which is incorporated by reference herein, discloses an interposer for joining a chip to a substrate. The interposer contains conductive plastic filled vias. Excess conductive plastic material is removed from the interposer with a so-called "doctor's knife".
Variot et al. U.S. Pat. No. 5,435,482, the disclosure of which is incorporated by reference herein, discloses the planarizing of solder balls on the bottom of an integrated circuit package in preparation for joining to a circuit board. The solder balls are planarized by pressing on a platen which may be heated. The solder balls are reflowed upon joining to the circuit board. The reference teaches that the solder balls are planarized to mitigate warpage or bowing of the integrated circuit package, as shown in FIG. 5 of the reference.
Liebman et al. U.S. Pat. No. 5,167,361, the disclosure of which is incorporated by reference herein, discloses the flattening of solder bumps on a printed circuit board in preparation for joining to a surface mounted component, e.g., an integrated circuit device. Flattening may be by a vice and platen or by cutting with a circular blade, saw or Q-cutter. Once the contact points of a surface mounted component make contact with the flattened solder, the solder is then reflowed.
McShane U.S. Pat. No. 4,661,192, the disclosure of which is incorporated by reference herein, discloses applying solder balls to an integrated circuit die, flattening the solder balls by pressing against a platen (the solder balls may be heated) and then joining the integrated circuit die to a die support frame by the use of conductive epoxy.
Gshwend U.S. Pat. No. 4,752,027, the disclosure of which is incorporated by reference herein, discloses that solder bumps are applied to a printed circuit board then flattened by a roller. A surface mountable component is placed on the flattened solder bumps and then the solder bumps are reflowed.
Granier et al. U.S. Pat. No. 5,324,892, the disclosure of which is incorporated by reference herein, discloses the joining of solder columns to a substrate. The columns are planarized so that they are all at the same height and then are joined to a second substrate by applying a further quantity of solder to the solder columns or the second substrate.
In view of the above, it is a purpose of the present invention to have an improved method for fabricating an electrical interconnection between a chip carrier and a semiconductor device having C-4 connections.